| 摘要 |
In a computer processor, multiple partially translated real addresses for a pipelined operation are compared with the real addresses of one or more other operations in the pipeline to detect an address conflict, without waiting for the address translation mechanism to fully translate the real address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and an N-way translation lookaside buffer (TLB) for determining the high-order portion of a real address. Each of the N real address portions in the TLB is compared with other operations in the pipeline, before determining which is the correct real address portion.
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