发明名称 |
Cryptographic accelerator |
摘要 |
A cryptographic accelerator ( 1 ) has a host interface ( 2 ) for interfacing with a host sending cryptographic requests and receiving results. A CPU ( 3 ) manages the internal logical unit in an exponentiation sub-system ( 7 ) having modulator exponentiators ( 30 ). The exponentiators ( 30 ) are chained together up to a maximum of four, in a block ( 20 ). There are ten blocks ( 20 ). A scheduler uses control registers and an input buffer to perform the scheduling control.
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申请公布号 |
US6963979(B2) |
申请公布日期 |
2005.11.08 |
申请号 |
US20020119851 |
申请日期 |
2002.04.11 |
申请人 |
AEP SYSTEMS LIMITED |
发明人 |
FAIRCLOUGH CHRISTOPHER;FLANAGAN FRANCIS |
分类号 |
G09C1/00;G06F7/72;(IPC1-7):G06F11/30;G06F12/14;H04L9/32 |
主分类号 |
G09C1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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