发明名称 |
Arbitration scheme for efficient parallel processing |
摘要 |
A system and method for assigning operations to multiple pipelines in a graphics system is disclosed. The graphics system may include an arbitration unit coupled to a plurality of calculation pipelines. The arbitration unit is operable to provide graphics operations to selected ones of the calculation pipelines. Each of the calculation pipelines is operable to perform a graphics operation. Each of the calculation pipelines may include digital logic and/or a processing element for performing the graphics operations. An operation may be assigned to a pipeline if the pipeline is performing a low latency operation. A low latency operation may comprise an operation that is performed by one of the calculation pipelines in less time than a pre-determined number of clock cycles.
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申请公布号 |
US6963342(B2) |
申请公布日期 |
2005.11.08 |
申请号 |
US20020085432 |
申请日期 |
2002.02.28 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
PASCUAL MARK E.;LAVELLE MICHAEL G.;RAMANI NANDINI;SHEHANE PATRICK |
分类号 |
G06F9/38;G06F15/78;G06T1/20;(IPC1-7):G06T1/20 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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