发明名称 Method for manufacturing chip scale package at wafer level
摘要 PURPOSE: A method for fabricating a chip scale package is provided to reduce the manufacturing cost by forming a lower insulation layer below a metallization layer. CONSTITUTION: A semiconductor wafer(40) is provided such that a chip cutting area is defined between a plurality of integrated circuit chips. An insulation film(26) is formed on a non active layer(14) of the semiconductor wafer(40). A metallization layer(17) is formed on the insulation film(26). The metallization layer(17) is connected to the chip pads(12). An upper insulation layer is formed on the metallization layer(17), the non active layer(14) and the insulation film(26). A ball pad(22) is made by partially cutting the upper insulation film(26). A solder ball(32) connected to the metallization layer(17) is formed in the ball pad(22). Then, the semiconductor wafer(40) is cut along the chip cutting area.
申请公布号 KR100526061(B1) 申请公布日期 2005.11.08
申请号 KR19990007882 申请日期 1999.03.10
申请人 发明人
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
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