发明名称 DIGITAL SIGNAL PROCESSING DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To reduce a circuit scale of an instruction decoder while reducing the number of instruction codes. <P>SOLUTION: A mode information holding part holds first or second mode information. A bit length converting part outputs by lengthening or shortening a bit length of input data. When the bit length is lengthened and the first mode information is held in the mode information holding part, the input data is closed up to a low-order side of an output bit length, and a highest-order bit value or 0 is input on a high-order side of the surplus output bit length. On the other hand, when the second mode information is held, the input data is closed up to the high-order side of the output bit length, and 0 is input on the low-order side of the surplus output bit length. When the bit length is shortened and the first mode information is held in the mode information holding part, a bit by the output bit length is extracted from a lowest-order bit of the input data, and on the other hand, when the second mode information is held in the mode information holding part, a bit by the output bit length is extracted from a highest-order bit of the input data. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005310051(A) 申请公布日期 2005.11.04
申请号 JP20040129799 申请日期 2004.04.26
申请人 TOSHIBA CORP 发明人 KOYAMA MITSUHIRO;ARAI YOSHIHISA
分类号 G06F7/00;G06F7/76;G06F9/34 主分类号 G06F7/00
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