发明名称 PROCESSOR
摘要 PROBLEM TO BE SOLVED: To dispense with a data arrangement instruction in advance of an arithmetic instruction in a SIMD type processor to improve arithmetic efficiency. SOLUTION: Matrix data are distributively stored in memory banks 310-313. The matrix data read from the memory banks 310-313 are rearranged and supplied to a computing element by reading control circuits 360, 370. Arithmetic results by the computing element are rearranged and written into the memory banks 310-313 by a writing control circuit 350. Address generation circuits 320-340 generate an address for longways or sideways scanning the matrix data distributively stored in the memory banks 310-313. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005309499(A) 申请公布日期 2005.11.04
申请号 JP20040121705 申请日期 2004.04.16
申请人 SONY CORP 发明人 HASEGAWA KOICHI
分类号 G06F9/34;G06F9/30;G06F9/302;G06F9/312;G06F9/315;G06F9/345;G06F12/00;G06F12/02;G06F12/06;G06F15/80;G06F17/16;(IPC1-7):G06F17/16 主分类号 G06F9/34
代理机构 代理人
主权项
地址