| 摘要 |
PROBLEM TO BE SOLVED: To clarify thread switching conditions when any cache mistake is caused when fetching an instruction, and to improve performance in a multi-thread system. SOLUTION: This thread switching controller is provided with a unit 3 for preparing an entry corresponding to a decoded instruction, and for erasing the entry when executing and completing the instruction, a means 5 for reporting the number of uncompleted instructions as the number of entries which have not been erased in the unit 3, and a means 4 for outputting a thread switching request signal when receiving such a report that the number of uncompleted instructions is 0 from the means 5 after any cache mistake is caused. COPYRIGHT: (C)2006,JPO&NCIPI
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