发明名称 EQUALIZER CIRCUIT APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide an equalizer circuit to process signals with a transmission band of several hundreds MHz or over. SOLUTION: The equalizer circuit apparatus comprises two signal processing circuits 1, 2, and the signal processing circuit 1 (2) includes: a delay line 12 (13) for delaying one differential signal; an adder circuit 14 (15) for receiving the other differential signal and an output signal from the delay line and summating the two signals at a different rate to provide a plurality of sum signals A, B; variable gain amplifiers 16, 17 (18, 19) for amplifying a plurality of the sum signals; and an adder 20 (21) for summating output signals from the variable gain amplifiers. Each of the adder circuits 20, 21 comprises a plurality of resistors connected in series. Through the configuration above, precise gain control and a high dynamic range are not required for the variable gain amplifiers, and the equalizer circuit to process a signal with several hundreds MHz is realized with components or a manufacturing technology available at present. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005311419(A) 申请公布日期 2005.11.04
申请号 JP20040121514 申请日期 2004.04.16
申请人 SHINKA SYSTEM SOGO KENKYUSHO:KK 发明人 KASAI YUJI
分类号 H03H11/04;H04B3/14;H04L25/03;(IPC1-7):H04B3/14 主分类号 H03H11/04
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