| 摘要 |
PROBLEM TO BE SOLVED: To provide a path delay test method which realizes test pattern generation allowing to detect a delay fault which is difficult to be detected by conventional test methods caused by speeding up of a semiconductor integrated circuit and miniaturization of processes and to allow high-quality products shipping without increasing development man-hour. SOLUTION: Critical paths for a guaranteed operation frequency and physical information such as wiring congestion and via density are extracted out of layout information generated by a net list of a semiconductor integrated circuit. On the basis of the physical information, trouble-prone parts are specified, and critical paths in which a delay fault is expected are selected from the critical paths. A test pattern is generated for only the selected critical path. For generating the test pattern, automatic test-pattern generating software is used. A weighting factor for the critical path is provided using a weighting inspection model obtained from critical path selecting information on the basis of the physical information. COPYRIGHT: (C)2006,JPO&NCIPI
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