| 摘要 |
<P>PROBLEM TO BE SOLVED: To efficiently decide a perfect conforming article LSI/a partially conforming article LSI/a defective LSI in an LSI test in a processor such as a CMP (Chip Multi-Processor) having a multi-core. <P>SOLUTION: The method is provided with an MISR (Multiple Input Signature Register) test pattern compression circuit for performing test pattern compression of the LSI test, out of a test pattern generating circuit by an LFSR (Linear Feedback Shift Register) and the test pattern compression circuit by the MISR which constitute a logic BIST (Built-In Self Test) circuit mounted on the processor, independently in each core part and CMP sharing part in order to perform efficient decision on the perfect conforming article LSI/the partially conforming article LSI/the defective LSI in the processor having the multi-core such as the CMP. Thus, simplification/speeding up of the decision of not only the perfectly conforming article LSI but also the partially conforming article LSI is aimed at, and improvement of yield by relief of the partially conforming article LSI at the time of semiconductor production and cost reduction are realized. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
