DIGITAL PROCESSOR APPARATUS WITH CODE COMPRESSION AND METHOD

摘要

A digital processor architecture and associated techniques for code compression particularly useful for, e.g., SOC or embedded applications where one or more constraints (such as memory size) are imposed. In one exemplary embodiment, the boundary between compressed and uncompressed code space is disposed between the instruction cache (408) and the processor core, the latter which is left completely unaware of compression and its functionality is fully preserved. Mechanisms are described that resolve the issues arising from the instruction cache data misalignment and the compressed to uncompressed address mapping. The compression techniques of the present invention reduce memory requirements for the IC design, which translates into savings in silicon cost. Alternatively, larger programs with additional functionality can be developed at the same cost compared to a corresponding system without invention. Reduced power consumption is also provided by the invention.