EFFICIENT MULTIPLICATION SEQUENCE FOR LARGE INTEGER OPERANDS WIDER THAN THE MULTIPLIER HARDWARE

摘要

A method of operating a multiplication circuit (21) to perform multiply-accumulate operations on multi­-word operands is characterized by an operations sequencer (23) that is programmed to direct the transfer of operand segments between RAM (15) and internal data registers (27; RX, RY, RZ, RR) in a specified sequence. The se­quence (e.g., Figs. 5A-5C) processes groups of two adja­cent result word-weights (columns), with the multiply cycles within a group proceeding in a zigzag fashion by alternating columns with steadily increasing or decreas­ing operand segment weights. In multiplier embodiments having additional internal cache registers (C_A0, C_ Al, C_B0, C_B1, C_B2), these store frequently used operand segments so they aren't reloaded from memory multiple times. In this case, the sequence within a group need not proceed in a strict zigzag fashion, but can jump to a multiply operation involving at least one operand segment stored in a cache.