| 摘要 |
A variable frequency synthesizer comprising a sigma-delta modulator is provided. Such synthesizers provide an exact average frequency whereas the instantaneous frequencies varies. The sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade. At least one input value of an accumulator (51, 52, 53, 54) being part of the sigma-delta modulator has a second component which is equal to an overflow signal (ofl, oft, of3, of4) multiplied by a factor. This feedback reduces the maximum fluctuation of the instantaneous frequencies. Phase jitter generated by non-linearities of the phase detector, the charge pump and the VCO is therefore reduced.
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