发明名称 Delay locked loop circuit
摘要 Disclosed is a delay locked loop circuit (DLL) used for DDR SDRAM. The DLL provides a fast locking function. In particular, the DLL detects the level of a frequency and performs the fast locking function, thereby realizing a high integrated memory device having a reduced area of a delay part used in order to synchronize a phase of an external clock signal with a phase of an internal clock.
申请公布号 US2005242855(A1) 申请公布日期 2005.11.03
申请号 US20050086054 申请日期 2005.03.22
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LEE JOONG HO
分类号 G11C8/00;H03L7/06;H03L7/07;H03L7/081;(IPC1-7):H03L7/06 主分类号 G11C8/00
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