| 摘要 |
<p>A method of manufacturing a thin film transistor array panel is provided, which includes forming a semiconductor layer of poly silicon, forming a gate insulating layer on the semiconductor layer, forming a conductive layer including a first metal layer and a second metal layer formed on the first metal layer, depositing and forming a photoresist pattern on the first and the second metal layer, forming a gate electrode by etching the conductive layer, wherein the gate electrode includes a double layered structure including the first metal layers having a narrower width than a width of the second metal layer, forming a source region and a drain region in the semiconductor layer by doping conductive impurities, ashing the photoresist pattern to expose a portion of the second metal, etching the exposed portion of the second metal layer, removing the photoresist pattern, and forming lightly doped drain regions having a lower concentration compared to the source region and the drain region by using the gate electrode as a doping mask.</p> |
