发明名称 Interconnection structure
摘要 An interconnect architecture is described in which a substrate such as a printed circuit board includes multiple conductive layers separated by one or more interposed insulating layers, the conductive layers being adapted to receive a high density array of interconnect elements such as a ball grid array (BGA). In certain preferred embodiments, a printed circuit board may provide a very low resistance interconnect forming the drain and source terminals of a lateral power MOSFET device incorporating a high density array of alternating source and drain interconnect elements, such as a BGA. In such embodiments, source and drain currents may be routed on different conductive layers separated by one or more interposed insulating layers. The upper conductive layer may include laterally non-conductive regions accommodating conductive columns that are connected to the lower conductive layer. <IMAGE>
申请公布号 EP1439581(A3) 申请公布日期 2005.11.02
申请号 EP20030258223 申请日期 2003.12.29
申请人 VLT, INC. 发明人 VINCIARELLI, PATRIZIO;STARENAS, PAUL V.;MCCAULEY, CHARLES I.
分类号 H01L21/60;H01L23/492;H01L23/498;H01L23/50;H05K1/02;H05K1/11;H05K3/34 主分类号 H01L21/60
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