发明名称 Circuit and method for generating a clock signal
摘要 In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a plurality of selectable delay circuits. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the oscillator circuit to activate one or more of the plurality of selectable delay circuits to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, processing the clock signal to generate a control signal, and activating one or more of a plurality of selectable delay circuits in the oscillator circuit, in response to the control signal.
申请公布号 US6960950(B2) 申请公布日期 2005.11.01
申请号 US20030400147 申请日期 2003.03.25
申请人 INTEL CORPORATION 发明人 SHAH PRASANNA C.;SCHNEIDER TOM J.;VOLK ANDREW M.;KELKAR MUKUL
分类号 H03L7/00;H03L7/06;H03L7/085;H03L7/099;(IPC1-7):H03L7/00 主分类号 H03L7/00
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