A method for controlling the enable interval of the signal controlling the data buses which connect both bit line sense amplifier and data sense amplifier according to the frequency variation of a memory device and the device thereof,申请号KR20040007912-传众专利搜索

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发明名称	A method for controlling the enable interval of the signal controlling the data buses which connect both bit line sense amplifier and data sense amplifier according to the frequency variation of a memory device and the device thereof
摘要
申请公布号	KR100525107(B1)	申请公布日期	2005.11.01
申请号	KR20040007912	申请日期	2004.02.06
申请人		发明人
分类号	G11C7/08;G11C7/00;G11C7/10;(IPC1-7):G11C7/08	主分类号	G11C7/08
代理机构		代理人
主权项
地址

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