发明名称 Semiconductor device having a lower parasitic capacitance
摘要 A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact-hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having lowerdielectric constant property, the parasitic capacitance can be reduced.
申请公布号 US6960808(B2) 申请公布日期 2005.11.01
申请号 US20030707358 申请日期 2003.12.08
申请人 PROMOS TECHNOLOGIES INC. 发明人 WANG YU-PIAO
分类号 H01L21/28;H01L21/336;H01L21/60;H01L21/768;H01L21/8234;H01L23/522;(IPC1-7):H01L29/76;H01L29/94;H01L31/062;H01L27/108;H01L31/113 主分类号 H01L21/28
代理机构 代理人
主权项
地址