Frequency detector detecting variation in frequency difference between data signal and clock signal

摘要

A reference clock signal or a clock signal delayed in phase from the clock signal by pi/2 is input to D input terminal of a flip-flop circuit. An FSM receives signals input to the flip-flop circuits and signals which have been held by the flip-flop circuits, and outputs an up signal and a down signal. The flip-flop circuits and the FSM operate in synchronization only with a rising edge of a data signal.