Power grid and bump pattern with reduced inductance and resistance

摘要

Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.