| 摘要 |
A MULTI-DIVIDE FREQUENCY DIVIDER, INCLUDES A CHAIN OF SERIALLY-CONNECTED FREQUENCY DIVIDER UNITS, EACH RESPONDING TO A FIRST STATE OF RECEIVED CONTROL SIGNALS BY USING THE REFERENCE CLOCK SIGNAL TO GENERATE AN OUTPUT SIGNAL HAVING A FREQUENCY THAT IS THE REFERENCE CLOCK FREQUENCY DIVIDED BY A FIRST DIVISOR, AND EACH RESPONDING TO A SECOND STATE OF THE CONTROL SIGNALS BY USING THE REFERENCE CLOCK SIGNAL TO GENERATE AN OUTPUT SIGNAL HAVING A FREQUENCY THAT IS THE REFERENCE CLOCK FREQUENCY DIVIDED BY A SECOND DIVISOR. THE OUTPUT SIGNAL MAY BE SUPPLIED TO A SUCCESSOR FREQUENCY DIVIDER UNIT IN THE CHAIN. DIVISION BY THE FIRST AND SECOND DIVISORS CAUSES THE FREQUENCY DIVIDER TO RESPECTIVELY TRANSITION THROUGH FIRST AND SECOND PREDETERMINED STATE SEQUENCES. EACH FREQUENCY DIVIDER FURTHER RESPONDS TO A THIRD STATE OF THE CONTROL SIGNALS BY INITIALIZING THE FREQUENCY DIVIDER TO AN INITIAL STATE THAT IS COMMON TO BOTH THE FIRST AND SECOND PREDETERMINED STATE SEQUENCES, WHEREBY THE FREQUENCY DIVIDER IN THE INITIAL STATE IS IMMEDIATELY RESPONSIVE TO SUBSEQUENT APPLICATION OF THE FIRST STATE OF THE CONTROL SIGNALS, AND IS IMMEDIATELY RESPONSIVE TO SUBSEQUENT APPLICATION OF THE SECOND STATE OF THE CONTROL SIGNALS. RECEIPT OF A RECEIVED SWALLOW ENABLE CONTROL SIGNAL HAVING A PREDETERMINED VALUE DISABLES DIVISION BY THE SECOND DIVISOR. EACH FREQUENCY DIVIDER FURTHER GENERATES AN OUTPUT CONTROL SIGNAL HAVING THE PREDETERMINED VALUE WHENEVER THE FREQUENCY DIVIDER IS IN THE INITIAL STATE.
|
