SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of guaranteeing a fast operation while soft error resistance is increased.

SOLUTION: This semiconductor memory device includes a memory cell formed in a silicon-on-insulator (SOI) substrate. The memory cell includes a plurality of n type resistance added transistors TN5 to TN8 in which a source and a drain are serially connected between the input nodes N1 and N2 and the output nodes N3 and N4 of a pair of inverters INV1 and INV2, and a pair of resistance added transistor groups TNG1 and TNG2 for interconnecting the pair of inverters INV1 and INV2. The n type resistance added transistors TN5 to TN8 are depression type transistors having threshold values equal to/less than 0, a gate is connected to a word line WL, and a conductive state is set between the source and the drain when a gate voltage is equal to a low potential power supply line VSS.

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