| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a local timer device being brought into a standby at an arbitrary timing synchronized with a high-speed clock, and providing a TSF timer value utilizing a low-speed clock equally to the case where the high-speed clock is continuously driven. <P>SOLUTION: A 1/40 counter 100 applies frequency dividing to the high-speed clock and supplies the divided clock to a TSF timer 102, and a TSF timer value 108 synchronized with timing is outputted from the TSF timer 102. The counting value of the 1/40 counter 100 is held in a register 110 synchronously with the low-speed clock in supplying the high-speed clock, and the TSF timer value 108 is held in a register 142. When the high-speed clock stops, two values calculated in response to a ratio between the high-speed clock and the low-speed clock are added to a held value of the register 110 at a predetermined probability by an adder 120 synchronously with the low-speed clock, and a value calculated in response to the ratio between the high-speed clock and the low-speed clock is added to the TSF timer value of a register 142 by an adder 150 every carry in the adder 120. When the high-speed clock re-operates, the held value of the register 110 is set in the 1/40 counter 100 at the first clock timing, and the held value of the register 142 is set in the TSF timer 102. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
