发明名称 Circuit to convert binary to ternary data based on ternary and quaternary logic has ternary full adder with pn binary or gates
摘要 <p>A circuit to convert binary into ternary data (40) based on ternary/quaternary logic comprises linking a ternary full adder (37) with PN binary OR gates (2). Four different potential levels give logic numbers 0,1,2,3 and are applied to the dual gates. Binary data are applied to the full adder and are converted to analog ternary values by OR gates.</p>
申请公布号 DE202005011873(U1) 申请公布日期 2005.10.27
申请号 DE20052011873U 申请日期 2005.07.21
申请人 TEVKUER, TALIP 发明人
分类号 G06F7/38;H03K19/00;H03M7/06;(IPC1-7):H03K19/00 主分类号 G06F7/38
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