发明名称 |
Half subtractor circuit based on ternary and quaternary logic combines input PNP OR-OR dual gates, with a arithmetically linked binary gates and a final ternary stage |
摘要 |
<p>Half subtractor (35) circuit comprises two PNP OR-OR dual gates (9), at the outputs of which are arithmetically linked binary gates (5, 7). The outputs of these are linked to a final ternary stage (17). The input to the first gate is a signal (A1) equal to the count value minus the minuend. The input to the second gate (B1) is equal to the count value minus the subtrahend.</p> |
申请公布号 |
DE202005011859(U1) |
申请公布日期 |
2005.10.27 |
申请号 |
DE20052011859U |
申请日期 |
2005.07.21 |
申请人 |
TEVKUER, TALIP |
发明人 |
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分类号 |
G06F7/38;G06F7/42;G06F7/49;H03K19/00;(IPC1-7):G06F7/42 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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