Clock signal distribution and interrupt system for microprocessor integrated circuit device - has number of global drivers uniformly disposed along periphery of integrated circuit and number of feeders for supply clock signals to circuit components of integrated circuit

摘要

The clock distribution system and clock interrupt system provides clock signals with less than (100) picoseconds of skew to various components of the integrated circuit (200) (ignoring effects associated with the matched stages), by using several stages of drivers (301,310-314, 30a-30l) to evenly supply the distributed clock signals. Each stage has RC matched input lines (e.g. 340-344). The matched stages and clock drivers are located within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other integrated circuit components and circuitry. The drivers can be selectively powered down in groups by a power management unit.