MEMORY CONTROLLER AND SEMICONDUCTOR DEVICE

摘要

A memory controller (121) is connected to an SRAM (122) which can be accessed only by a row address and an NOR-type flash memory and to an SDRAM (124) which can be accessed by specifying a row address and a column address. A data bus (107) is shared by time division and the other control lines are individually connected to the SRAM (122), the NOR-type flash memory (123), and the SDRAM (124). An access request for each of the memory devices as the access destination is accumulated in a FIFO memory (201). A data bus idle section which cannot be accessed by the SDRAM (124) is detected by an SDRAM access section judgment device (204). If an access request to the SRAM (122) following the access-disabled section can be executed, the access request order in the FIFO memory (201) is changed so that the access request to the SRAM (122) is placed at the head.