Ternary erase and read memory based on ternary and quaternary logic has pnp or or dual gate address decoder and four logic values

摘要

A ternary erase and read memory (42) based on ternary and quaternary logic comprises an address decoder (44) after a PNP-logic OR-OR dual gate (9) whose output, controlled by two N-channel MOS transistors (V), passes to an end stage (17). Four different potential levels forming logic numbers 0,1,2,3 are applied to the gate.