IMAGE PROCESSOR

摘要

An image processor is provided to increase a speed of entire image processing by efficiently operating a CPU. In the image processor (1), a high-speed bus (10) and a peripheral bus (12) are connected via a bus bridge (11). The CPU (13) for performing calculation and control of image processing, a data transmitting/receiving FIFO memory (18) for transmitting and receiving image compression data to and from a host device (4), a frame memory (16) for storing image decompression data from an electronic camera (2), etc. and displaying the data on a display panel (3), and a compression/decompression circuit (17) for compressing the image decompression data and decompressing the image compression data are connected to the both buses (10, 12). The CPU (13) and the frame memory (16) are connected to the high-speed bus (10), and the data transmitting/receiving FIFO memory (18) is connected to the peripheral bus (12).