发明名称 |
СПОСОБ ПЕРЕДАЧИ И ПРИЕМА ИНФОРМАЦИИ ДЛЯ ОБНАРУЖЕНИЯ ОШИБКИ В СИСТЕМЕ СВЯЗИ |
摘要 |
Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence. An initial value controller provides the registers with a selected one of two initial values separately determined for the two data sequences. <IMAGE> |
申请公布号 |
RU2004113955(A) |
申请公布日期 |
2005.10.27 |
申请号 |
RU20040113955 |
申请日期 |
2004.05.06 |
申请人 |
САМСУНГ ЭЛЕКТРОНИКС КО., ЛТД. (KR) |
发明人 |
КИМ Донг-Хее (KR);ЧОЙ Хо-Киу (KR);КИМ Йоун-Сун (KR);КВОН Хван-Дзоон (KR) |
分类号 |
H03K3/84;G06F1/00;H03M13/09;H04B7/216;H04L1/00;H04L1/08;H04L1/20;H04L1/22 |
主分类号 |
H03K3/84 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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