| 摘要 |
PROBLEM TO BE SOLVED: To shorten a development period and to reduce man-days for development by reducing remarkably man-days for regenerating a test pattern, a verification program or expectation data, even if timing is shifted by a partial change of the verification program or the like, especially when a semiconductor integrated circuit is operated synchronously with a plurality of inside operation clocks, concerning a verification device and a verification method of the semiconductor integrated circuit. SOLUTION: The timing when the plurality of operation clocks inside the semiconductor integrated circuit have a prescribed phase relation is detected by a phase relation detection circuit, and a trigger signal is outputted, and an input timing of a test pattern, a start timing of the verification program and a comparison timing with the expectation data are used as a relative timing based on a trigger timing. COPYRIGHT: (C)2006,JPO&NCIPI
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