Datenverarbeitungssystem mit Befehlspipeline

摘要

A data processing system having a pipeline is provided which includes a CPU designed to fetch a plurality of instructions simultaneously from a memory through a data bus in an instruction fetching stage. Each of the instructions is expressed in a string of bits having a bit length which is shorter than a bus width of the data bus. The instruction fetching stage is effected every instruction processing cycles of a number equal to the number of the instructions simultaneously fetched from the memory for a period of time during which instruction decoding stages of a number equal to the number of simultaneously fetched instructions are effected in the instruction processing cycles in succession. This enables high-speed pipelined operations.