| 摘要 |
PROBLEM TO BE SOLVED: To provide a subfield coding circuit for realizing both reduction of a memory capacity required for storing a translation table and high operation speed. SOLUTION: The subfield coding circuit 30 according to this invention includes one memory cell array 31 for storing two or more words corresponding to respective subfield data, a group of address decoders 32a to 32c for simultaneously selecting R, G, B selection words from among the two or more words to the respective data in response to respective R, G, B gradation data 21a to 21c, and a reading port 33. The memory cell array 31 supplies the R, G, B selection words to the reading port 33 simultaneously as the R, G, B subfield data 22a to 22c corresponding to the respective gradation data 21a to 21c. The reading port (33) outputs the R, G, B subfield data (22a to 22c). COPYRIGHT: (C)2006,JPO&NCIPI
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