Reconfigurable matrix multiplier architecture and extended borrow parallel counter and small-multiplier circuits

摘要

A dynamically or run-time reconfigurable matrix multiplier architecture with a reconfiguration mechanism for computing the product of matrices Xpxr and Yrxq for any integers p, q, r and any item precision b, i.e., bitwidth, ranging from 4 to 64 bits is described. The reconfigurable matrix multiplier uses borrow parallel counters with new circuits, 6 _- 0 , and 6 _- 1 and the improved small multiplier library. The reconfigurable matrix multiplier architecture is based on a novel scheme of trading data bitwidth for processing array or matrix size. The matrix multiplier achieves an extra compact, low power, high speed design through the use of a borrow parallel counters and a library of small borrow parallel multiplier circuits. The matrix multiplying processor using area comparable with a single 64x64-b multiplier constructed of very large-scale integrated (VLSI) circuits, can be reconfigured to produce the product of two matrices X(4x4) and Y(4x4) of 8, 16, and 32-bit data items in every 1, 4, and 16 pipeline cycles, respectively, or the product of two 64-b numbers in every pipeline cycle.