发明名称 |
ANALOGUE/DIGITAL DELAY LOCKED LOOP |
摘要 |
There is disclosed a delay locked loop (300) comprising: a digital delay circuit (302) which enables digital delay elements (400) to provide coarse phase adjustment during initialization in the delay locked loop (300); a counter (308) configured to control the number of the digital delay elements (400) enabled; and an analog delay circuit (304) which provides, after coarse phase adjustment is completed, a fine phase adjustment in the delay locked loop (300), and wherein the analog delay circuit (304) employs a variable control signal during the fine phase adjustment. |
申请公布号 |
EP1588489(A1) |
申请公布日期 |
2005.10.26 |
申请号 |
EP20030785447 |
申请日期 |
2003.12.29 |
申请人 |
MOSAID TECHNOLOGIES INCORPORATED |
发明人 |
VLASENKO, PETER;HAERLE, DIETER |
分类号 |
H03D3/24;H03L7/081;H03L7/087;H03L7/089;H03L7/095;H03L7/10;(IPC1-7):H03L7/087 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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