Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output

摘要

A programmable skew clock signal generator has a frequency generator circuit ( 104 ) consistent with the invention produces an output signal F_phi0 from a reference signal F_ref A frequency accumulator ( 132, 152 ) is preloaded with a preload value P_K1 and receives one reference signal cycle as a clock signal, receives a constant K₁ as an input thereto, with the frequency accumulator ( 132, 152 ) having a maximum count K_MAX and producing an overflow output. A phase accumulator ( 136, 156 ) is preloaded with a preload value P_C1 and receives one overflow cycle output from the frequency accumulator ( 132, 152 ) as a clock signal and receives a phase offset constant C₁ as an input thereto. The phase accumulator ( 136, 156 ) has a maximum count C_MAX and produces a phase accumulator ( 136, 156 ) output. A delay line ( 320 ) is clocked by the reference signal F_ref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit ( 140, 144; 160, 164 ) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output F_phi1 whose phase shift phi₁ relative to F_0phi is a function of P_K1 and P_C1.