发明名称 |
Data latch with low-power bypass mode |
摘要 |
A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.
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申请公布号 |
US6958624(B1) |
申请公布日期 |
2005.10.25 |
申请号 |
US20030437426 |
申请日期 |
2003.05.12 |
申请人 |
ALTERA CORPORATION |
发明人 |
STARR GREGORY;LANGHAMMER MARTIN;HWANG CHIAO KAI |
分类号 |
H03K3/012;H03K3/037;(IPC1-7):H03K19/177 |
主分类号 |
H03K3/012 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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