发明名称 Circuit and method for generating a clock signal
摘要 In some embodiments, a circuit includes an oscillator circuit, a control circuit, and a synchronization circuit. The oscillator circuit generates a clock signal and includes a selectable delay circuit. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the synchronization circuit which provides a control signal that has been synchronized to the oscillator circuit to activate the selectable delay circuit to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, and synchronizing activation of a selectable delay circuit in the oscillator circuit to a local clock signal.
申请公布号 US6958658(B2) 申请公布日期 2005.10.25
申请号 US20030400146 申请日期 2003.03.25
申请人 INTEL CORPORATION 发明人 SHAH PRASANNA C.;KELKAR MUKUL
分类号 H03B1/00;H03B27/00;(IPC1-7):H03B27/00 主分类号 H03B1/00
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