发明名称 Single stage, level restore circuit with mixed signal inputs
摘要 A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.
申请公布号 US6958629(B2) 申请公布日期 2005.10.25
申请号 US20040769257 申请日期 2004.01.30
申请人 INTEL CORPORATION 发明人 WIJERATNE SAPUMAL
分类号 H03K19/00;H03K19/0185;(IPC1-7):H03K19/00 主分类号 H03K19/00
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