发明名称 |
Memory device with reduced cell size |
摘要 |
A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.
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申请公布号 |
US6958269(B2) |
申请公布日期 |
2005.10.25 |
申请号 |
US20020178100 |
申请日期 |
2002.06.24 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MITROS JOSEF CZESLAW;KHAN IMRAN;SPRINGER LILY |
分类号 |
H01L21/28;H01L29/423;(IPC1-7):H01L21/236;H01L29/745 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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