发明名称 Slew rate controlling method and system for output data
摘要 A slew rate controlling system for output data is provided which is capable of improving an output data window even when change in a potential difference between a first power supply (VDD) to be used for outputting and a second power supply (VDDQ) to be used internally occurs. The slew rate controlling system is achieved by using a VDD-VDDQ potential difference detecting circuit to detect a decrease in a potential difference between the first power supply (VDD) and the second power supply (VDDQ) and to produce a first signal with specified timing and to detect an increase in a potential difference between the first power supply (VDD) and the second power supply (VDDQ) and to produce a second signal and by using a slew rate controlling circuit to exert control, when the first signal is significant, to enlarge a transition speed in a fall of output data and to exert control, when the second signal is significant, to enlarge the transition speed in a rise of output data and to produce output data.
申请公布号 US6958638(B2) 申请公布日期 2005.10.25
申请号 US20030681836 申请日期 2003.10.09
申请人 ELPIDA MEMORY, INC. 发明人 SHIBATA TOMOYUKI;OISHI KANJI
分类号 H03K5/12;G11C11/409;H03K17/687;H03K19/003;H03K19/0175;(IPC1-7):H03K3/017 主分类号 H03K5/12
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