| 摘要 |
PROBLEM TO BE SOLVED: To provide a sequential circuit and a logic synthesis circuit capable of surely reducing power consumption without shifting synchronous timing. SOLUTION: This sequential circuit is provided with a first holding circuit 1 for synchronizing with a first clock signal CP and holding an input signal IN, a second holding circuit 2 for synchronizing with a second clock signal G_CP and holding a hold signal of the first holding circuit 1, and a clock generation circuit 3 for generating the second clock signal G_CP only when the hold signal of the first holding circuit 1 is difference from a hold signal of the second holding circuit in logic. Since the second holding circuit 2 performs a holding operation only when the hold signal of the first holding circuit 1, that is, the next signal that should be held by the second holding circuit 2 is different from the present hold signal of the second holding circuit in logic, the number of holding times of the second holding circuit 2 can be reduced and the power consumption of the second holding circuit 2 can be reduced. COPYRIGHT: (C)2006,JPO&NCIPI
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