发明名称 |
Semiconductor memory device |
摘要 |
In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.
|
申请公布号 |
US2005232038(A1) |
申请公布日期 |
2005.10.20 |
申请号 |
US20050151417 |
申请日期 |
2005.06.14 |
申请人 |
HASEGAWA MASATOSHI;KAJIGAYA KAZUHIKO |
发明人 |
HASEGAWA MASATOSHI;KAJIGAYA KAZUHIKO |
分类号 |
G11C11/401;G11C7/00;G11C29/00;G11C29/02;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|