CLOCK RECOVERY IN AN OVERSAMPLED SERIAL COMMUNICATIONS SYSTEM

摘要

The present invention relates to the recovery of a clock from the parallel data bits in an over-sampling receiver and a method using the same. A high-speed receiver according to the invention comprises a sampling system which provides a set of samples of the received signal; provided with a multiphase clock generator; and a dual phase detector PLL configured with a clock recovery phase detector, a phase and frequency detector and a lock detector; wherein the frequency lock detector determines when lock is achieved, and once achieved, switches the phase detector to the clock recovery phase detector which extracts the frequency of the data from the over-sampled data to generate signals to achieve the clock recovery.