Successive approximation analog/digital converter with reduced chip area

摘要

A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.