Systems and methods for reconfigurable computing

摘要

A processing system includes a communication bus, a controller, an Input/Output ("I/O") block, and reconfigurable logic segments (e.g., reconfigurable units). Individually reconfigurable logic segments are part of a single chip. A communication bus is in electrical communication with the logic segments. A first logic segment communicates to a second logic segment over the communication bus. Reconfiguration can partition a first logic segment into a second and a third logic segment where the smaller logic segments are in electrical communication with the communication bus. Resources are dynamically reallocated when reconfigurable units are either combined or partitioned. More specifically, both partitioning a logic segment and combining two or more logic segments can change the bus width allocated to a reconfigurable unit and the quantity of logic gates in the reconfigured unit. The embedded resources included in a logic segment can also change as a result of reconfiguration. The processing system provides high chip utilization throughout the chip's operation.