DELTA-SIGMA MODULATION TYPE FRACTIONAL FREQUENCY DIVISION PLL FREQUENCY SYNTHESIZER, AND RADIO COMMUNICATION APPARATUS

摘要

PROBLEM TO BE SOLVED: To suppress an increase in circuit scale and to suppress the generation of a spurious tone.

SOLUTION: The delta-sigma modulation type fractional frequency division PLL frequency synthesizer performs fractional frequency division by modulating a frequency divider 37 for performing the frequency division of an output frequency of a voltage controlled oscillator 35. Fractional part data F from a register 42 are sent to a second adder 43. A first adder 41 generates pseudorandom bitstreams, the average value of which is zero by adding an output of a delta-sigma converter 44 to a resulting one obtained by delaying and inverting the output in a delay inverter 40. The second adder 43 generates a pseudorandom data sequence, the average value of which is the value of the fractional part data by adding the fractional part data F to an output of the first adder 41 and sends the data sequence to a delta-sigma modulator 44. An adder 38 adds integral part data to an output of the delta-sigma modulator 44 and sends the added output to the frequency divider 37.

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