发明名称 Memory system including a circuit to convert between parallel and serial bits
摘要 A memory controller comprises a circuit to convert a set of parallel constituent bits to a serial stream of constituent bits. A first output driver receives at least four bits of the serial stream of constituent bits in succession from the circuit. The first output driver outputs the at least four bits of the serial stream of constituent bits onto a first external signal line.
申请公布号 US2005232020(A1) 申请公布日期 2005.10.20
申请号 US20050151792 申请日期 2005.06.14
申请人 PEREGO RICHARD E;WARE FREDRICK A 发明人 PEREGO RICHARD E.;WARE FREDRICK A.
分类号 G06F12/00;G06F13/12;G06F13/16;G11C16/06;(IPC1-7):G11C16/06 主分类号 G06F12/00
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