发明名称 Semiconductor integrated circuit device and test method thereof
摘要 Disclosed is a semiconductor integrated circuit device using a scan path test in which propagation of an indefinite value to a test target path is inhibited while suppressing an increase in a circuit area, and a test method thereof. When a plurality of flip-flops within a logic circuit is serially connected to form scan chains and a scan path test is conducted, one or a plurality of flip-flops within the logic circuit are provided as indefinite state control flip-flops for holding values for preventing an indefinite value from propagating through a test target path and being captured by the scan chain on an output side during the test. The indefinite state control flip-flops are serially connected based on a control signal, and constitute a chain of flip-flops, different from the scan chain of other flip-flops. A value serially input from an input terminal is set in the plurality of indefinite state control flip-flops, respectively.
申请公布号 US2005235184(A1) 申请公布日期 2005.10.20
申请号 US20050108642 申请日期 2005.04.19
申请人 NEC ELECTRONICS CORPORATION 发明人 YAMAUCHI HISASHI
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F11/22;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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